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HS-6617RH-T
Data Sheet July 1999 File Number
4608.1
Radiation Hardened 2K x 8 CMOS PROM
Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HS-6617RH-T is a radiation hardened 16k CMOS PROM, organized in a 2K word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, and is designed to be functionally equivalent to the HM-6617. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. On chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structure, such as the HS-80C86RH. The output enable control (G) simplifies microprocessor system interfacing by allowing output data bus control, in addition to, the chip enable control. Synchronous operation of the HS-6617RH-T is ideal for high speed pipe-lined architecture systems and also in synchronous logic replacement functions.
Features
* QML Class T, Per MIL-PRF-38535 * Radiation Performance - Gamma Dose () 1 x 105 RAD(Si) - SEU LET 16MeV/mg/cm2 - SEL LET 100MeV/mg/cm2 * Field Programmable Nicrome Fuse Links * Low Standby Power 1.1mW Max * Low Operating Power 137.5mW/MHz Max * Fast Access Time 100ns Max * TTL Compatible Inputs/Outputs * Synchronous Operation * On Chip Address Latches, Three-State Outputs
Pinouts
HS1-6617RH-T (SBDIP), CDIP2-T24 TOP VIEW
A7 A6 A5 A4 A3 A2 A1 A0 Q0 1 2 3 4 5 6 7 8 9 24 VDD 23 A8 22 A9 21 P 20 G 19 A10 18 E 17 Q7 16 Q6 15 Q5 14 Q4 13 Q3
Specifications
Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HS-6617RH-T are contained in SMD 5962-95708. A "hot-link" is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil's Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp
Q1 10 Q2 11 GND 12
HS9-6617RH-T (FLATPACK), CDFP4-F24 TOP VIEW
A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD A8 A9 P G A10 E Q7 Q6 Q5 Q4 Q3
Ordering Information
ORDERING NUMBER 5962R9570801TJC HS1-6617RH/Proto 5962R9570801TXC HS9-6617RH/Proto PART NUMBER HS1-6617RH-T HS1-6617RH/Proto HS9-6617RH-T HS9-6617RH/Proto TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
P must be hardwired at all times to VDD, except during
programming.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HS-6617RH-T Functional Diagram
A10 A9 A8 A7 A6 A5 A4 MSB 7 LATCHED ADDRESS REGISTER LSB E P E 8 16 16 16 16 16 16 16 16 8 Q0 - Q7 7 A A GATED ROW DECODER 128 1 OF 8 128 x 128 MATRIX
GATE COLUMN DECODER PROGRAMMING, AND DATA
E E A G
OUTPUT CONTROL 4 A 4
E
LATCHED ADDRESS REGISTER MSB A3 A2 A1 A0 LSB
ALL LINES POSITIVE LOGIC: ACTIVE HIGH THREE STATE BUFFERS: OUTPUT ACTIVE A HIGH
ADDRESS LATCHES & GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G P = HARDWIRED TO VDD EXCEPT DURING PROGRAMMING
TRUTH TABLE E 0 0 1 G 0 1 X MODE Enabled Output Disabled Disabled
Timing Waveform
TAVQV 3.0V 1.5V 1.5V VALID ADDRESS ADDRESSES TELEL TAVEL TELAX TELEH 3.0V 1.5V E TEHEL G 1.5V TGLQX TELQX VALID DATA TS TELQV TGLQV 1.5V 0V TGHQZ TEHQZ 3.0V 1.5V 1.5V 1.5V 0V VALID ADDRESSES 0V
DATA OUTPUT Q0 - Q7
FIGURE 1. READ CYCLE
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HS-6617RH-T Die Characteristics
DIE DIMENSIONS: (4166m x 6350m x 483m 25.4m) 164 x 250 x 19mils 1mil METALLIZATION: Type: Silicon - Aluminum Thickness: 13.0kA 2kA SUBSTRATE POTENTIAL: VDD BACKSIDE FINISH: Silicon PASSIVATION: Type: Silox (SiO2) Thickness: 8.0kA 1kA WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 PROCESS: SSAJIIV-RH
Metallization Mask Layout
HS-6617RH-T
(24)VDD (23) A8 (22) A9 (5) A3 (4) A4 (3)A5 (2) A6 (1) A7 (21) P
(20) G A2 (6) (19) A10
A1 (7) A0 (8) GND (12) Q1 (10) Q2 (11) Q3 (13) Q4 (14) Q5 (15) Q6 (16) Q7 (17) Q0 (9)
(18) E
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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